1. Field of the Invention
The present invention relates to a process of producing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor, and, more particularly, to a structure of an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up.
2. Description of the Prior Art
The LDMOS (Laterally Diffused Metal-Oxide Semiconductor) is usually used in high-voltage integrated circuits and may generally be manufactured using some of the same techniques used to fabricate the low voltage circuitry or logic circuitry. Hence, a commonly used high-voltage element for these circuits is the laterally diffused Metal-Oxide transistor (LDMOS). Conventional LDMOS structures are first discussed to establish a basic understanding of the present invention.
For example, FIG. 1 shows a cross-sectional view of the structure of a conventional LDMOS transistor. The LDMOS transistor has a P-type substrate 10, a V-shaped trench 11, a P-type body region 12, a N.sup.+ drain region 15, gate oxide 16, and an oxide layer 17. In this structure, the V-shaped trench 11 is used to reduce the dimension of the entire LDMOS transistor.
The N.sup.+ source region 13, the P-type body region 12, and the P-type substrate 10 form a vertical parasitic PNP transistor. And the vertically projecting area of the N.sup.+ source region 13 is relatively large, thus the leakage caused by the parasitic PNP transistor is relatively large and its propensity to cause latch-up problems is a drawback.